1. Field of the Invention
The current invention generally relates to soft error rates in static random access (SRAM) memories. More in particular, the current invention relates to reducing soft error rate in SRAM memories.
2. Description of the Related Art
Electronic systems, and in particular computer systems, typically store a relatively large amount of information in static random access (SRAM) memories on one or more semiconductor chips. For example, a modern computer system might have a 128 KB (128 Kilobytes) of SRAM in a level-1 instruction cache, 128 KB in a level-1 data cache, and 2 MB (Megabytes) in a level-2 cache on a processor chip. Some electronic systems such as computer systems have one or more SRAM chips separate from a logic chip where the logic chip accesses data in the SRAM chips.
SRAM memory cells, i.e., the semiconductor devices on a semiconductor chip that store the “1”s and “0”s used in an SRAM are typically constructed of a number of field effect transistors (FETs), such as N-channel field effect transistor, NFET 1, shown in a side view in FIG. 1. Gate 2 is typically formed of a polysilicon material, and is often silicided (e.g., with titanium to make titanium silicide) to lower resistance of the gate. A thin gate oxide 3 separates gate 2 from an area 9 between a source 5 and a drain 4. NFET 1, and other FETs are formed on a semiconductor substrate, such as substrate 6, formed, in the exemplary drawing of FIG. 1, as a P-doped semiconductor.
During operation of an SRAM, the semiconductor chip is bombarded with high energy particles. For example, lead is often used for solder and other interconnection metallurgy, such as solder bumps used to connect a semiconductor chip to a module. Lead is subject to radioactive decay, resulting in alpha particles. A path 7 of a high energy particle (e.g., an alpha particle) is shown in FIG. 1. As the particle passes through the semiconductor, ionization of the semiconductor occurs, forming negative charges and positive charges. Substrate 6, shown as a P-material for exemplary purposes, is typically coupled to ground. Positive charges formed are attracted to and swept to the ground. Negative charges are similarly attracted to higher voltage regions on the semiconductor chip. Many NFET drains on a chip are at a high voltage, and negative charges will be swept to those drains. In an SRAM memory cell, constructed of two cross coupled inverters, each inverter made of an NFET and a P-channel FET (PFET), one inverter output is a “0” (gnd) and the other is at “1” (a positive supply voltage). FETs (PFETs and NFETs) in an SRAM cell are designed to be very small, in order to pack as many SRAM cells as possible into a given area. Because of the small widths of the FETs, the outputs of the inverters have relatively high impedance. A particle strike at or near an NFET drain may lower the voltage of the NFET drain to a voltage lower than a critical voltage that will cause the cell to change state as a result of the particle strike. A similar situation exists for PFETs. PFETs are placed in an N-well that is coupled to a positive voltage. A particle strike again causes ionization. Negative charges are swept to the positive voltage coupled to the N-well; positive charges are swept to lower voltages in the area of the particle strike, such as a PFET drain that is at “0”. Analogous to the strike near the NFET drain described above, a particle strike near a PFET drain can raise the voltage of the PFET drain; if the PFET drain (i.e., an inverter output in an SRAM cell) is raised above a critical voltage, the SRAM cell will flip to the wrong value. The actual amount of charge swept to a node depends on the energy of the high energy particle, where it strikes relative to the node, and characteristics of the semiconductor.
A number of techniques have been used to reduce SRAM memory cells from being changed erroneously by particle strikes. These unwanted changes are called soft errors, and the rate they occur is called a soft error rate (SER).
A first technique used to reduce SER places resistors of relatively high value between the output of each inverter and the input of the other. This slows the regeneration of the latch in the SRAM memory cell, and allows the inverter that suffered the particle strike to recover before the voltage on the output of the inverter that suffered the high energy particle strike can propagate to the input of the other inverter and cause the other inverter to also change its output. Unfortunately, high value resistors in semiconductor structures tend to be relatively large. Also, they typically have a relatively large amount of parasitic capacitance that slows the process of writing data into the SRAM memory cell. Slower regeneration also degrades performance when writing operations to the SRAM memory cell.
A second technique to reduce SER adds capacitance coupled to the output of each inverter in the SRAM memory cell. Since a particle strike tends to cause a particular number of charged particles to be swept to the affected drain, and, since V=q/C, where V is voltage change, q is charge introduced by the ionization and swept to the affected drain, and C is capacitance, a larger capacitance translates into a smaller voltage change at the drain. However, adding capacitors causes a less dense SRAM memory cell, as well as poorer performance.
SOI (Silicon On Insulator) semiconductor technology dramatically reduces SER, but is a more expensive semiconductor process.
Adding ECC (Error Correction Code) provides for correction of soft errors, but increases the size of the array and can add delay to the read and write operations.
Using a higher voltage supply to the SRAM helps to reduce SER, but a higher fixed supply voltage results in higher power. Modern electronic systems and their semiconductor chips are becoming limited in performance by thermal limits. Coupling the chip or chips, including the SRAM, to a fixed supply voltage that is at or near a maximum allowable voltage for the chip is undesirable from a power and thermal standpoint.
Therefore, there is a need for a method and apparatus that provide for a reduction in SER without significantly increasing power dissipation, using a more expensive semiconductor process, or slowing performance of an SRAM.